This invention relates to a frequency synthesizer comprising a reference frequency generator coupled to a frequency control circuit which includes a variable frequency reduction means including a cycle cancellation circuit which is arranged to cancel a cycle of the frequency to be reduced by the reduction means for each input pulse to said cycle cancellation circuit from an offset frequency generator arranged to produce n pulses for each group of x pulses of a given frequency Fr to provide a variable offset frequency (n/x)Fr where n is any integer smaller than x, and further comprising a jitter compensation signal circuit connected to the frequency control circuit, an output of the jitter compensation signal circuit being arranged such that a compensation signal at the output causes compensation, at least partly, for any jitter in the period of the output frequency of the synthesizer that would otherwise be caused as a result of each cancelled cycle, which jitter compensation signal circuit derives the compensation signal as a function of the offset frequency via an analogue integrator.
Such a frequency synthesizer is described in United Kingdom Patent Application No. 8208094.
Frequency synthesizers to which the invention is applicable are either of the "direct" type in which the output frequency is derived directly from the reference frequency or of the "indirect", or phase locked loop, type in which the output frequency is generated by a voltage-controlled variable frequency oscillator forming part of a phase lock loop which locks the oscillator frequency to a predetermined rational fraction (which is to be understood herein as including a multiple) of the reference frequency.
In each type of frequency synthesizer, the cancellation of a cycle of the frequency to be reduced would, if preventive steps were not taken, produce a resultant jitter in the period of the output frequency. To prevent this, the compensation signal circuit produces a compensation signal which is a function of the offset frequency--i.e. the pulse train which in fact causes the jitter in the first place. The compensation signal is derived from these pulses by first removing their d.c. content, by a high pass filter for example, and then integrating the pulses to produce an analogue compensation signal.
If d.c. removal is accomplished by a high pass filter network, then to avoid distortion of the pulse train the filter time constant must be significantly larger than the period of the lowest frequency offset that can be introduced. The problem associated with this is that, in general, the d.c. level of the pulse train is different for different offset frequencies so that when the offset frequency is changed there is a period of time (proportional to the filter time constant) during which the (d.c.-blocking) capacitor in the high pass filter holds the incorrect voltage. This has the effect of temporarily distorting the compensation signal until the capacitor charges up or discharges to the correct d.c. level. For example, if the lowest offset frequency is 10 Hz then for the best final spectral purity the filter time constant should be of the order of one second. This will lead to unwanted spurii at the output of the synthesizer for about ten seconds after changing the offset frequency. Thus, there is a conflict between the final spectral purity of the output frequency and the speed with which this can be achieved after a frequency change.